| Architecture | Dual-core TMS320C28x 32-bit CPUs, each running at 200 MHz. Includes IEEE 754 single-precision Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and Viterbi/Complex Math Unit (VCU-II). |
| Control Law Accelerators (CLAs) | Two programmable CLAs operating at 200 MHz, capable of executing IEEE 754 single-precision floating-point instructions independently of the main CPUs. |
| Memory | 1 MB (512K x 16) of flash memory with ECC protection and 204 KB (102K x 16) of RAM with ECC or parity protection. |
| System Peripherals | Two External Memory Interfaces (EMIFs) supporting ASRAM and SDRAM, dual 6-channel Direct Memory Access (DMA) controllers, and up to 169 individually programmable GPIO pins with input filtering. |
| Communication Interfaces | USB 2.0 (MAC + PHY), two Controller Area Network (CAN) modules, three high-speed SPI ports, two Multichannel Buffered Serial Ports (McBSPs), four Serial Communications Interfaces (SCI/UART), and two I2C interfaces. |
| Analog Subsystem | Up to four Analog-to-Digital Converters (ADCs) supporting 16-bit mode at 1.1 MSPS each (up to 4.4 MSPS system throughput) with differential inputs, and 12-bit mode at 3.5 MSPS each (up to 14 MSPS system throughput) with single-ended inputs. Also includes eight windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references and three 12-bit buffered DAC outputs. |
| Enhanced Control Peripherals | 24 Pulse Width Modulator (PWM) channels with enhanced features, 16 High-Resolution PWM (HRPWM) channels, six Enhanced Capture (eCAP) modules, three Enhanced Quadrature Encoder Pulse (eQEP) modules, and eight Sigma-Delta Filter Module (SDFM) input channels. |
| Configurable Logic Block (CLB) | Augments existing peripheral capabilities and supports position manager solutions. |
| Functional Safety Compliance | Developed for functional safety applications with documentation available to aid ISO 26262 system design up to ASIL D; IEC 61508 up to SIL 3; IEC 60730 up to Class C; and UL 1998 up to Class 2. Hardware integrity up to ASIL B, SIL 2. |
| Package | 337-ball New Fine Pitch Ball Grid Array (nFBGA) measuring 16x16 mm. |
| Operating Temperature Range | -40°C to 105°C junction temperature. |
Texas Instruments